Any mention and/or discussion of the prior art throughout the specification should not be considered, in any way, as an admission that this prior art is well known or forms part of common general knowledge in the field.
Amongst other resistive memories, Spin-Transfer-Torque-Magnetic RAM (STT-MRAM) is widely considered as the most promising candidate for future non-volatile embedded memories [2], [1]. The memory bitcell typically consists of Magnetic Tunnel Junction (MTJ) 100 driven by an access transistor 102 (see FIG. 1). The MTJ 100 serves as a memory element, as it can operate in the parallel (P) or antiparallel (AP) state, as determined by the relative direction of the magnetization of the MTJ Free layer (FL) compared to the MTJ Pinned layer (PL). Since the resistance of the MTJ 100 is lower at P and higher at AP, data stored in the bitcell is retrieved by sensing the difference in the MTJ 100 resistance.
A number of sensing schemes have been proposed to implement for STT-MRAMs, which are either voltage sensing, [4]-[6], or current sensing [7]-[13] schemes (i.e., by sensing either the current or the voltage across the bitline).
The current sensing circuit was first introduced in [7] with adopting a symmetrical current averaging reference generator. Many enhancements and modifications have been subsequently proposed in [7]-[13]. Particularly, source degeneration and body biasing for mitigating impacts of process variation in the data path was presented in [8] and [9], respectively. Offset canceling techniques, which seek to eliminate the mismatch between data sensing and reference path, were multiply proposed in [10]-[13], typically by introducing one or more sampling stages.
Techniques of dual reference and dynamic reference have been subsequently mentioned in [12] and [13] for the current sensing scheme. Authors in [13] actually introduced after-testing optimization for the reference value to attain optimum bit error rate (BER). Similarly, the work in [12] proposed a dual reference scheme where the reference voltage can also be dynamically selected by controlling a programmable multiplexer after acquiring the statistical data of the memory array. Current sensing generally exhibits better robustness than voltage sensing, as its read BER under variations can be approximately as low as the intrinsic bitcell error rate which is known to be an absolute lower bound. However, current sensing is known to be unsuited for operation at voltages lower than nominal, thus prohibiting energy reductions through voltage scaling [5].
Conventional voltage sensing (CVS) [5] method in contrast to counterpart current sensing does not attain as good BER as current sensing. However, the scheme is more suitable for low-power and low voltage applications. The work in [5] introduced a self-referenced voltage sensing scheme that performs a destructive read involving four steps of successive read/write, at the cost of substantially increased energy per access and access time. A non-destructive self-reference scheme was proposed in [6] by exploiting the high roll-off slope of the MTJ resistance in AP state as a function of its bias voltage. This scheme still uses multiple read steps, and is effective only under large critical switching current (200-500 μA), which makes it unsuitable for technologies below 90 nm. Furthermore, the work in [5] proposed boosted voltage sensing, which amplifies the bitline voltage using a simple switched-cap voltage booster. The circuit not only achieves the low BER (at the order of 1E-9) but shows relatively good performance across the practical voltage range (0.7V-1.2V) [3] of STT-MRAMs.
Other proposed approaches are briefly described in the following.                1. Dual Reference Cell Sensing Scheme for Non-Volatile Memory [14] (JIANQ CHYUN Intellectual Property Office, Taiwan, 2004), US Pat. Publ. No. 2004/0264249 A1 proposes a circuit for non-volatile memory with dual reference and two-stage amplifying, which attains high robustness to process variation. At the first stage, the bitcell sampling current is compared to high and low reference by two adjustable bias amplifiers. The output of the first stage amplifiers is sent to second stage amplifier to determine the final readout value. The main drawback of this scheme is to double the first amplifying stage, thus, consume large energy and area.        2. Self-Reference Sense amplifier for Spin Transfer Torque [15] (Everspin Technologies, Inc., 2013), US Pat. Publ. No. US 2013/0272060 A1 proposes a sensing scheme without requiring external reference, involving three stages. At the first stage MTJ state is sampled (into a capacitor) then at the second stage the cell is overwritten (by a known value) before the bitcell is sampled again for generating the reference. At the third stage, readout bit is determined by comparing the sampled voltage to the reference. This scheme performs destructive read which eventually requires an additional write back stage (the fourth stage), thus, consuming extremely large energy (since writing is an energy-consuming operation for STT-MRAM [1]-[3]) and degrading the overall performance.        3. Body Voltage Sensing Based on Short Pulse Reading Circuit [16] (University of California, 2014), U.S. Pat. No. 8,917,562 B2 proposes a modification on the sensing circuit in [8] where the body of the PMOS biasing transistor is connected to the sampling output. This was quantitatively proven to mitigate the process variation impact on the sensing node, and hence, improve the read-ability. Since this proposed circuit follows the traditional current sensing scheme, it essentially still suffers from larger energy consumption and is unsuited for low voltage operations.        4. Symmetrical Differential Sensing Method and System for STT-MRAM [17] (Infineon Technologies AG, 2015), US Pat. Publ. No. US 2014/0056059 A1 proposes a circuit and current sensing method for STT-MRAMs where reference and data subsequently go through the same sampling phases and paths (sense and inverse sense). Consequently, the offset between reference and data paths is theoretically canceled. The drawback of this scheme is the multi-stage sensing, which degrades the read performance and consumes more energy.        5. Mismatch Error Reduction Method and System for STT MRAM [18] (Infineon Technologies AG, 2014), US Pat. Publ. No. US 2014/0063923 A1 proposes a circuit and current sensing method for STT-MRAMs where an additional sampling phase is introduced in order to record to offset voltage of reference and data sensing path. This offset value is stored in a capacitor and is then used to compensate the offset between the two paths during the actual sensing phase. The proposed sensing method is still based on the current sensing scheme and requires dual stage sensing and the stored offset value may not be accurate enough under low voltage operations. The main drawback of this scheme is the requirement for extra sensing stages, which result in high energy and poorer performance.        6. Differential Sensing Method and System for STT-MRAM [19] (Infineon Technologies AG, 2014), U.S. Pat. No. 8,837,210 B2 proposes a circuit for sensing STT-MRAM cell where the reference and sampling current is fed through the same set of transistors without using current mirror, thus, eliminating the mismatch of reference and sensing current. The proposed method has similar disadvantages in performance and energy as in [16], [17], i.e., requires multi-stage sensing and is not suitable for low-voltage operations.        
Embodiments of the present invention seek to address at least one of the above problems.